ATPG targets faults at IC-gate boundaries, but 50% of defects are located within cells. Learn how cell-aware ATPG and user-defined fault models help to ferret out these hard-to-squash bugs.

With small-scale CMOS technology nodes, the probability of physical defects occurring in the device increases. Various defects occur which cannot be detected with the help of conventional Single Stuck ...

Once IC fabrication is complete, engineers use fault models to create test patterns that detect defects. These fault models are typically abstractions of defect behavior based on our experience and ...

The IDDQ test relies on measuring the supply current (I DD) of an IC’s quiescent state, when the circuit isn’t switching and inputs are held at static values. Test patterns are used to place the ...